The present invention relates generally to packaging of integrated circuits (IC), and, more specifically, to a system for dispensing an underfill between an IC chip and a substrate.
Integrated circuits (ICs) are circuits formed on a semiconductor wafer. Prior to being used in an electronic device, the IC must be packaged to protect the IC from being damaged. The package also provides connectors or pins for connecting the IC to other devices. A large variety of IC package configurations and technologies have been developed. Examples of IC package configurations include in-line packages, small outline packages, quad flat pack packages, pin grid array packages, ball grid array packages, and flip chip ball grid array packages. Each packaging technology provides a combination of characteristics such as packaging efficiency, lead count, thermal performance, electrical performance, size, weight, flexibility, and reliability.
Flip chip ball grid array (FCBGA) package configuration is an advanced packaging technology that aids in making the size of the package compact. In an FCBGA package, an IC chip is mounted in an upside-down manner over a substrate, and is electrically coupled to the substrate through multiple bumps provided on an active surface of the IC chip. However, gaps are left between the IC chip and the substrate. Since the IC chip and the substrate have different coefficients of thermal expansion (CTE), any thermal stress generated due to high-temperature conditions may result in breaking or damaging the bumped electrical connections. Therefore, to maintain the reliability of the FCBGA package, it is important to fill the gaps between the IC chip and the substrate.
The gaps between the IC chip and the substrate are usually filled with a non-conductive underfill material such as epoxy and resin. The underfill material protects the bumps from dust, moisture, etc., and provides additional mechanical strength to the IC package. Further, the underfill material between the IC chip and the substrate improves the reliability of the IC package by spreading the thermal stress generated due to the CTE mismatch over the entire area of the IC chip, instead of just over the bumps. Generally, the underfill material is injected between the IC chip and the substrate using a dispenser. The underfill material is then drawn into the gaps by capillary action.
Efficiency of an underfill process is primarily determined by the time required to dispense the underfill material between the IC chip and the substrate. The filling time of the underfill material is further affected by various other factors such as driving force required for dispensing the underfill material and surface friction during the flow of the underfill material. For example, in the dispensing method described above, the surface tension between the bumps is the driving force for the underfill material. However, the surface tension may not be sufficient enough to evenly distribute the underfill material in the gaps. Further, some gaps may still remain unfilled due to the lack of sufficient surface tension required for driving the underfill material. This also may prolong the filling time. Long filling time results in the formation of air bubbles within the gaps that may weaken the structure of the IC package. Further, the method mentioned above does not take into consideration the surface friction during the flow of the underfill material, which further prolongs the filling time. Another important factor in determining the filling time is the viscosity of the underfill material. The viscosity is defined as a measure of the resistance of a fluid to flow. However, the viscosity of the underfill material changes with temperature and the change affects the flow of the underfill material.